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LTC1416 Low Power 14-Bit, 400ksps Sampling ADC FEATURES
s s s s s s s s s s s
DESCRIPTIO
Sample Rate: 400ksps Power Dissipation: 70mW Guaranteed 1.5LSB DNL, 2LSB INL (Max) 80.5dB S/(N + D) and 93dB THD at 100kHz 80dB S/(N + D) and 90dB THD at Nyquist Nap and Sleep Shutdown Modes Operates with Internal or External Reference True Differential Inputs Reject Common Mode Noise 15MHz Full Power Bandwidth Sampling 2.5V Bipolar Input Range 28-Pin SSOP Package
The LTC (R)1416 is a 2.2s, 400ksps, 14-bit sampling A/D converter that draws only 70mW from 5V supplies. This easy-to-use device includes a high dynamic range sampleand-hold and a precision reference. Two digitally selectable power shutdown modes provide flexibility for low power systems. The LTC1416's full-scale input range is 2.5V. Maximum DC specifications include 2LSB INL, 1.5LSB DNL over temperature. Outstanding AC performance includes 80.5dB S/(N + D) and 93dB THD with a 100kHz input, and 80dB S/(N + D) and 90dB THD at the Nyquist input frequency of 200kHz. The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 15MHz bandwidth. The 60dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The ADC has a P compatible, 14-bit parallel output port. There is no pipeline delay in the conversion results. A separate convert start input and a data ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors.
APPLICATI
s s s s s s
S
Telecommunications Digital Signal Processing Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATI
10F AVDD DVDD
Complete, 70mW, 14-Bit ADC with 80.5dB S/(N + D)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1k
Effective Bits and Signal-to-(Noise + Distortion) vs Input Frequency
86 80 74 68 62 SIGNAL/(NOISE + DISTORTION) (dB)
LTC1416 AIN+ S/H AIN- REFCOMP 22F VREF 1F VSS 10F -5V BUFFER 4k 2.5V REFERENCE TIMING AND LOGIC 14-BIT ADC 14
EFFECTIVE BITS
OUTPUT BUFFERS
* * *
D13 (MSB) D0 (LSB)
BUSY CS CONVST RD SHDN
fSAMPLE = 400kHz 10k 100k INPUT FREQUENCY (Hz) 1M 2M
1416 TA02
AGND
DGND
1416 TA01
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NYQUIST FREQUENCY
UO
UO
1
LTC1416 ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO
TOP VIEW AIN+ 1 AIN- 2 VREF 3 REFCOMP 4 AGND 5 D13(MSB) 6 D12 7 D11 8 D10 9 D9 10 D8 11 D7 12 D6 13 DGND 14 28 AVDD 27 DVDD 26 VSS 25 BUSY 24 CS 23 CONVST 22 RD 21 SHDN 20 D0 19 D1 18 D2 17 D3 16 D4 15 D5
AVDD = DVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ................................................ 6V Negative Supply Voltage (VSS)................................ - 6V Total Supply Voltage (VDD to VSS) .......................... 12V Analog Input Voltage (Note 3) ......................... (VSS - 0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 4) ..........(VSS - 0.3V) to 10V Digital Output Voltage ....... (VSS - 0.3V) to (VDD + 0.3V) Power Dissipation ............................................. 500mW Operating Temperature Range Commercial ............................................ 0C to 70C Industrial ........................................... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER LTC1416CG LTC1416IG
G PACKAGE 28-LEAD PLASTIC SSOP
TJMAX = 110C, JA = 95C/W
Consult factory for Military grade parts and for A grade parts.
CO VERTER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco (Note 8) (Note 7) CONDITIONS
With Internal Reference (Notes 5, 6)
MIN
q q q q
TYP 0.8 0.7 5 20 10 15
MAX 2 1.5 20 60 40
UNITS Bits LSB LSB LSB LSB LSB ppm/C
13
Internal Reference External Reference = 2.5V IOUT(REF) = 0
A ALOG I PUT
SYMBOL PARAMETER VIN IIN CIN t ACQ t AP tjitter CMRR
(Note 5)
CONDITIONS 4.75V VDD 5.25V, - 5.25V VSS - 4.75V CS = High Between Conversions During Conversions (Note 9)
q q q
MIN
TYP 2.5
MAX 1
UNITS V A pF pF
Analog Input Range (Note 9) Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio
15 5 100 -1.5 2 400
psRMS dB
- 2.5V < (AIN-
= AIN+ ) < 2.5V
60
2
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ns ns
W
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WW
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LTC1416
DY A IC ACCURACY
SYMBOL S/(N + D) THD SFDR IMD PARAMETER
I TER AL REFERE CE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance COMP Output Voltage CONDITIONS IOUT = 0 IOUT = 0 4.75V VDD 5.25V - 5.25V VSS - 4.75V - 0.1mA IOUT 0.1mA IOUT = 0
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL PARAMETER VIH VIL IIN CIN VOH High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage VDD = 4.75V IOUT = - 10A IOUT = - 200A VDD = 4.75V IOUT = 160A IOUT = 1.6mA VOUT = 0V to VDD, CS High CS High (Note 9 ) VOUT = 0V VOUT = VDD CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD
VOL
Low Level Output Voltage
IOZ COZ ISOURCE ISINK
Hi-Z Output Leakage D13 to D0 Hi-Z Output Capacitance D13 to D0 Output Source Current Output Sink Current
POWER REQUIRE E TS
SYMBOL PARAMETER VDD VSS IDD Positive Supply Voltage Negative Supply Voltage Positive Supply Current Nap Mode Sleep Mode Negative Supply Current Nap Mode Sleep Mode
ISS
UW
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WU U
(Note 5)
CONDITIONS 100kHz Input Signal 200kHz Input Signal 100kHz Input Signal, First 5 Harmonics 200kHz Input Signal, First 5 Harmonics 100kHz Input Signal fIN1 = 87.01172kHz, fIN2 = 113.18359kHz (S/(N + D) 77dB)
q q q
MIN 77
TYP 80.5 80 - 93 - 90 - 95 - 90 15 0.8
MAX
UNITS dB dB
Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth
- 86 - 86
dB dB dB dB MHz MHz
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(Note 5)
MIN 2.480 TYP 2.500 15 0.05 0.05 4 4.06 MAX 2.520 UNITS V ppm/C LSB/V LSB/V k V
(Note 5)
MIN
q q q
TYP
MAX 0.8 10
UNITS V V A pF V V V V A pF mA mA
2.4
5 4.5
q
4.0 0.05 0.10
q q q
0.4 10 15
- 10 10
(Note 5)
CONDITIONS (Note 10) (Note 10)
q
MIN 4.75 - 4.75
TYP
MAX 5.25 - 5.25
UNITS V V mA mA A mA A A
SHDN = 0V, CS = 0V SHDN = 0V, CS = 5V
q
7 0.8 1 7 20 15
10 1.2 10
SHDN = 0V, CS = 0V SHDN = 0V, CS = 5V
3
LTC1416
POWER REQUIRE E TS
SYMBOL PDISS PARAMETER Power Dissipation Power Dissipation, Nap Mode Power Dissipation, Sleep Mode
TI I G CHARACTERISTICS
SYMBOL fSAMPLE(MAX) tCONV tACQ tACQ+CONV t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time Acquisition + Conversion Time CS to RD Setup Time CS to CONVST Setup Time CS to SHDN Setup Time SHDN to CONVST Wake-Up Time CONVST Low Time CONVST to BUSY Delay Data Ready Before BUSY
Delay Between Conversions Wait Time RD After BUSY Data Access Time After RD
t11
Bus Relinquish Time
t12 t13
RD Low Time CONVST High Time
The q denotes specifications which apply over the full operating temperature range; all other limits and typicals at TA = 25C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND and AGND wired together unless otherwise noted. Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or above VDD without latchup. Note 4: When these pin voltages are taken below VSS, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, VSS = - 5V, fSAMPLE = 400kHz, t r = t f = 5ns unless otherwise specified.
4
UW
(Note 5)
CONDITIONS
q
MIN
TYP 70 4 0.1
MAX 100 6
UNITS mW mW mW
SHDN = 0V, CS = 0V SHDN = 0V, CS = 5V
UW
(Note 5, see Figures 15 to 21)
CONDITIONS
q q
MIN 400 1.5
TYP 1.9 100 2
MAX 2.2 400 2.5
UNITS kHz s ns s ns ns ns
(Note 9) (Notes 9, 10) (Notes 9, 10) (Notes 9, 10) (Note 10) (Notes 10, 11) CL = 25pF
q q q q q
0 10 10 400 40 25 50 75 50 40 -5 15 25 35 35 50 20 25 30 100
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
q q q
(Note 10) CL = 25pF
q q q
CL = 100pF
q
20 8
q q q q
0C TA 70C - 40C TA 85C
t 10 40
Note 6: Linearity, offset and full-scale specifications apply for a singleended AIN+ input with AIN- grounded. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from - 0.5LSB when the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The falling CONVST edge starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For best results ensure that CONVST returns high either within 900ns after the start of the conversion or after BUSY rises.
LTC1416 TYPICAL PERFORMANCE CHARACTERISTICS
S/(N + D) vs Input Frequency and Amplitude
90 VIN = 0dB
SIGNAL-TO-NOISE RATIO (dB)
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
SIGNAL/(NOISE + DISTORTION) (dB)
80 70 60 50 40 30 20 10 0 1k 10k 100k INPUT FREQUENCY (Hz) 1M 2M
1416 G01
VIN = -20dB
VIN = -60dB
Spurious-Free Dynamic Range vs Input Frequency
0
SPURIOUS-FREE DYNAMIC RANGE (dB)
0 -20 -40 -60 -80
-10 -20 AMPLITUDE (dB) -30 -40 -50 -60 -70 -80 -90 1k 10k 100k INPUT FREQUENCY (Hz) 1M 2M
1416 G04
DNL ERROR (LSB)
-100
Integral Nonlinearity vs Output Code
1.0
0
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
-20 -30 -40 -50 -60 -70 -80 -90 1k DGND (VIN = 100mV) VSS (VIN = 10mV) VDD (VIN = 10mV) 10k 100k RIPPLE FREQUENCY (Hz) 1M 2M
1416 G08
COMMON MODE REJECTION (dB)
VOUT = 2.5V VREF = 2.5V
0.5
INL ERROR (LSB)
0
-0.5
-1.0
0
4096
8192 OUTPUT CODE
12288
UW
1416 G07
Signal-to-Noise Ratio vs Input Frequency
90 80 70 60 50 40 30 20 10 0 1k 10k 100k INPUT FREQUENCY (Hz) 1M 2M
1416 G02
Distortion vs Input Frequency
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 1k 10k 100k INPUT FREQUENCY (Hz) 1M 2M
1416 G03
THD
3RD 2ND
Intermodulation Distortion Plot
1.0
fSAMPLE = 400kHz fa=87.01171876kHz fb=113.1835938kHz
Differential Nonlinearity vs Output Code
VOUT = 2.5V VREF = 2.5V
0.5
0
-100 -120 -140 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (Hz)
1416 G05
-0.5
-1.0
0
4096
8192 OUTPUT CODE
12288
16384
1416 G06
Power Supply Feedthrough vs Ripple Frequency
80 70 60 50 40 30 20 10 0 -10
Input Common Mode Rejection vs Input Frequency
-100
16384
1k
10k 100k INPUT FREQUENCY (Hz)
1M 2M
1416 G09
5
LTC1416
PI FU CTIO S
AIN+ (Pin 1): 2.5V Positive Analog Input. AIN- (Pin 2): 2.5V Negative Analog Input. VREF (Pin 3): 2.5V Reference Output. Bypass to AGND with 1F. REFCOMP (Pin 4): 4.06V Reference Output. Bypass to AGND with 22F tantalum in parallel with 0.1F ceramic, or 22F ceramic. AGND (Pin 5): Analog Ground. D13 to D6 (Pins 6 to 13): Three-State Data Outputs. DGND (Pin 14): Digital Ground for Internal Logic. Tie to AGND. D5 to D0 (Pins 15 to 20): Three-State Data Outputs. SHDN (Pin 21): Power Shutdown Input. Low selects shutdown. Shutdown mode selected by CS. CS = 0 for nap mode and CS = 1 for sleep mode. RD (Pin 22): Read Input. This enables the output drivers when CS is low. CONVST (Pin 23): Conversion Start Signal. This active low signal starts a conversion on its falling edge. CS (Pin 24): The Chip Select input must be low for the ADC to recognize CONVST and RD inputs. CS also sets the shutdown mode when SHDN goes low. CS and SHDN low select the quick wake-up nap mode. CS high and SHDN low select sleep mode. BUSY (Pin 25): The BUSY output shows the converter status. It is low when a conversion is in progress. Data is valid on the rising edge of BUSY. VSS (Pin 26): - 5V Negative Supply. Bypass to AGND with 10F tantalum in parallel with 0.1F ceramic, or 10F ceramic. DVDD (Pin 27): 5V Positive Supply. Tie to Pin 28. AVDD (Pin 28): 5V Positive Supply. Bypass to AGND with 10F tantalum in parallel with 0.1F ceramic, or 10F ceramic.
FU CTIO AL BLOCK DIAGRA
AIN+ CSAMPLE AIN- 4k VREF 2.5V REF ZEROING SWITCHES
REF AMP
REFCOMP (4.06V) AGND DGND INTERNAL CLOCK
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CSAMPLE AVDD DVDD VSS
+
14-BIT CAPACITIVE DAC COMP
-
14 OUTPUT LATCHES
SUCCESSIVE APPROXIMATION REGISTER
* * *
D13 D0
CONTROL LOGIC
SHDN CONVST
RD
CS
BUSY
1416 BD
LTC1416
TEST CIRCUITS
Load Circuits for Access Timing
5V 1k DBN 1k CL DBN CL DBN 1k 100pF DBN 100pF
Load Circuits for Output Float Delay
5V 1k
(A) Hi-Z TO VOH AND VOL TO VOH
(B) Hi-Z TO VOL AND VOH TO VOL
1416 TC01
(A) VOH TO Hi-Z
(B) VOL TO Hi-Z
1416 TC02
APPLICATIONS INFORMATION
CONVERSION DETAILS The LTC1416 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 14-bit parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.)
CSAMPLE+ HOLD AIN- SAMPLE HOLD CDAC+ CSAMPLE- HOLD ZEROING SWITCHES HOLD
AIN+
SAMPLE
+
VDAC+ CDAC- COMP
-
VDAC- SAR 14
OUTPUT LATCH
Figure 1. Simplified Block Diagram
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Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun, it cannot be restarted. During the conversion, the internal differential 14-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the AIN+ and AIN- inputs are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum delay of 400ns will provide enough time for the sample-and-hold capacitors to acquire the analog signal. During the convert phase the comparator zeroing switches open, putting the comparator into compare mode. The input switches connect the CSAMPLE capacitors to ground, transferring the differential analog input charge onto the summing junction. This input charge is successively compared with the binary-weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the differential DAC output balances the AIN+ and AIN- input charges. The SAR contents (a 14-bit data word) which represents the difference of AIN+ and AIN- are loaded into the 14-bit output latches.
* * *
D13 D0
1416 F01
7
LTC1416
APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE The LTC1416 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to test the ADC's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. Figure 2 shows a typical LTC1416 FFT plot.
0 -20 AMPLITUDE (dB)) -40 -60 -80 -100 -120 -140 0 fSAMPLE = 400kHz fIN = 101.5625kHz SFDR = 95.2dB SINAD = 80.5dB
25
50
75
100 125 150 175 200
1416 F02a
FREQUENCY (kHz)
Figure 2a. LTC1416 Nonaveraged, 4096 Point FFT, Input Frequency = 100kHz
0 EFFECTIVE BITS -20 -40 -60 -80 -100 -120 -140 0 fSAMPLE = 400kHz fIN = 189.9414kHz SFDR = 94.8dB SINAD = 80.2dB
AMPLITUDE (dB))
25
50
100 125 150 175 200 FREQUENCY (kHz) 75
1416 F02b
Figure 2b. LTC1416 Nonaveraged, 4096 Point FFT, Input Frequency = 190kHz
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Signal-to-Noise Ratio The Signal-to-Noise plus Distortion Ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 2a shows a typical spectral content with a 400kHz sampling rate and a 100kHz input. The dynamic performance is excellent for input frequencies up to and beyond the Nyquist limit of 200kHz, Figure 2b. Effective Number of Bits The Effective Number of Bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: ENOB = [S/(N + D) - 1.76]/6.02 where ENOB is the Effective Number of Bits of resolution and S/(N + D) is expressed in dB. At the maximum sampling rate of 400kHz the LTC1416 maintains near ideal ENOBs up to the Nyquist input frequency of 200kHz (refer to Figure 3).
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1k 86 80 74 68 62
SIGNAL/(NOISE + DISTORTION) (dB)
NYQUIST FREQUENCY
fSAMPLE = 400kHz 10k 100k INPUT FREQUENCY (Hz) 1M 2M
1416 TA02
Figure 3. Effective Bits and Signal/(Noise + Distortion) vs Input Frequency
LTC1416
APPLICATIONS INFORMATION
Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as:
THD = 20 log V22 + V32 + V42 + ...Vn2 V1
AMPLITUDE (dB)
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through Nth harmonics. THD versus input frequency is shown in Figure 4. The LTC1416 has good distortion performance up to the Nyquist frequency and beyond.
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 1k 10k 100k INPUT FREQUENCY (Hz) 1M 2M
1416 G03
THD
3RD 2ND
Figure 4. Distortion vs Input Frequency
Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and differ-
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ence frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: IMD fa + fb = 20 log
0 -20 -40 -60 -80 fSAMPLE = 400kHz fa=87.01171876kHz fb=113.1835938kHz
(
)
Amplitude at fa + fb Amplitude at fa
(
)
-100 -120 -140 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (Hz)
1416 G05
Figure 5. Intermodulation Distortion Plot
Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. The full-linear bandwidth is the input frequency at which the S/(N + D) has dropped to 77dB (12.5 effective bits). The LTC1416 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter's Nyquist frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist.
9
LTC1416
APPLICATIONS INFORMATION
Driving the Analog Input The differential analog inputs of the LTC1416 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN- input is grounded). The AIN+ and AIN- inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC1416 inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 6). For minimum acquisition time, with high source impedance, a buffer amplifier should be used. The only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 400ns for full throughput rate).
10
ACQUISITION TIME (s)
1
0.1
0.01 10
100 1k 10k SOURCE RESISTANCE ()
100k
1416 F06
Figure 6. Acquisition Time vs Source Resistance
Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (<100) at the closed-loop bandwidth
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frequency. For example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 50MHz, then the output impedance at 50MHz should be less than 100. The second requirement is that the closed-loop bandwidth must be greater than 10MHz to ensure adequate smallsignal settling for full throughput rate. If slower op amps are used, more settling time can be provided by increasing the time between conversions. The best choice for an op amp to drive LTC1416 will depend on the application. Generally, applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC1416. More detailed information is available in the Linear Technology Databooks and the LinearViewTM CD-ROM. LT (R)1220: 30MHz unity-gain bandwidth voltage feedback amplifier. 5V to 15V supplies, excellent DC specifications. LT1223: 100MHz video current feedback amplifier. 6mA supply current, 5V to 15V supplies, low distortion at frequencies above 400kHz, low noise, good for AC applications. LT1227: 140MHz video current feedback amplifier. 10mA supply current, 5V to 15V supplies, lowest distortion at frequencies above 400kHz, low noise, best for AC applications. LT1229/LT1230: Dual and quad 100MHz current feedback amplifiers. 2V to 15V supplies, low noise, good AC specs, 6mA supply current each amplifier. LT1360: 50MHz voltage feedback amplifier. 3.8mA supply current, good AC and DC specs, 5V to 15V supplies. LT1363: 70MHz, 1000V/s op amps. 6.3mA supply current, good AC and DC specs. LT1364/LT1365: Dual and quad 70MHz, 100V/s op amps. 6.3mA supply current per amplifier.
LinearView is a trademark of Linear Technology Corporation.
LTC1416
APPLICATIONS INFORMATION
Input Filtering The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1416 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 15MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 7 shows a 1000pF capacitor from AIN+ to ground and a 200 source resistor to limit the input bandwidth to 800kHz. The 1000pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can also generate distortion from self-heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems.
ANALOG INPUT 200 1000pF 1 2 3 4 22F 5 AIN+ AIN- LTC1416 VREF REFCOMP AGND
1416 F07
Figure 7. RC Input Filter
Input Range The 2.5V input range of the LTC1416 is optimized for low noise and low distortion. Most op amps also perform best over this same range, allowing direct coupling to the analog inputs and eliminating the need for special translation circuitry. Some applications may require other input ranges. The LTC1416 differential inputs and reference circuitry can
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accommodate other input ranges often with little or no additional circuitry. The following sections describe the reference and input circuitry and how they affect the input range. Internal Reference The LTC1416 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500V. It is connected internally to a reference amplifier and is available at VREF (Pin 3). See Figure 8a. A 4k resistor is in series with the output so that it can be easily overdriven by an external reference or other circuitry (see Figure 8b). The reference amplifier gains the voltage at the VREF pin by 1.625 to create the required internal reference voltage. This provides buffering between the VREF pin and the high speed capacitive DAC. The
2.5V
3
VREF
R1 4k
BANDGAP REFERENCE
4.0625V
4
REFCOMP R2 80k
REF AMP
22F 5 AGND
LTC1416 R3 128k
1416 F08a
Figure 8a. LTC1416 Reference Circuit
5V VIN LT1019A-2.5 VOUT ANALOG INPUT
1 2 3 4 22F 5
AIN+ AIN- LTC1416 VREF REFCOMP AGND
1416 F08b
Figure 8b. Using the LT1019-2.5 as an External Reference
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LTC1416
APPLICATIONS INFORMATION
COMMON MODE REJECTION (dB)
reference amplifier compensation pin, REFCOMP (Pin 4), must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 1F or greater. For the best noise performance, a 22F ceramic or 22F tantalum in parallel with a 0.1F ceramic is recommended. The VREF pin can be driven with a DAC or other means shown in Figure 9. This is useful in applications where the peak input signal amplitude may vary. The input span of the ADC can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. The filtering of the internal LTC1416 reference amplifier will limit the bandwidth and settling time of this circuit. A settling time of 5ms should be allowed for after a reference adjustment.
1 ANALOG INPUT 1.25V TO 3V 2 3 4 22F 5 AIN+ AIN- LTC1416 VREF REFCOMP
LTC1450
AGND
1416 F09
Figure 9. Driving VREF with a DAC
Differential Inputs The LTC1416 has a unique differential sample-and-hold circuit that allows rail-to-rail inputs. The ADC will always convert the difference of AIN+ - AIN- independent of the common mode voltage. The common mode rejection holds up to extremely high frequencies (see Figure 10a). The only requirement is that both inputs cannot exceed the AVDD or AVSS power supply voltages. Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are independent of the common mode voltage, however, the bipolar zero error (BZE) will vary. The change in BZE is typically less than 0.1% of the common mode voltage. Dynamic performance is also affected by the common mode voltage. THD will degrade as the inputs approach either power supply rail, from 90dB with a common mode of 0V to 79dB with a common mode of 2.5V or - 2.5V. Differential inputs allow greater flexibility for accepting different input ranges. Figure 10b shows a circuit that
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80 70 60 50 40 30 20 10 0 1k 10k 100k INPUT FREQUENCY (Hz) 1M 2M
1416 G09
Figure 10a. CMRR vs Input Frequency
1 2 2.5V 3 0V TO 5V 4 22F 5
ANALOG INPUT
AIN+ AIN- VREF LTC1416
REFCOMP AGND
1416 F10b
Figure 10b. Selectable 0V to 5V or 2.5V Input Range
converts a 0V to 5V analog input signal with no additional translation circuitry. Full-Scale and Offset Adjustment Figure 11a shows the ideal input/output characteristics for the LTC1416. The code transitions occur midway between successive integer LSB values (i.e., - FS + 0.5LSB, - FS + 1.5LSB, - FS + 2.5LSB, . . . FS - 1.5LSB, FS - 0.5LSB). The output is two's complement binary with 1LSB = FS - (- FS)/16384 = 5V/16384 = 305.2V. In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before full-scale error. Figure 11b shows the extra components required for full-scale error adjustment. Zero offset is achieved by adjusting the offset applied to the AIN- input. For zero offset error, apply - 152V (i.e., - 0.5LSB) at AIN+ and adjust the offset at the AIN- input until the output code flickers between 0000
LTC1416
APPLICATIONS INFORMATION
0000 0000 00 and 1111 1111 1111 11. For full-scale adjustment, an input voltage of 2.499544V (FS/2 - 1.5LSB) is applied to AIN and R2 is adjusted until the output code flickers between 0111 1111 1111 10 and 0111 1111 1111 11.
011...111 011...110 OUTPUT CODE
000...001 000...000 111...111 111...110 100...001 100...000 - (FS - 1LSB) FS - 1LSB
1416 F11a
INPUT VOLTAGE (AIN+ - AIN-)
Figure 11a. LTC1416 Transfer Characteristics
-5V R1 50k R3 24k
ANALOG INPUT
1 2
AIN+ AIN- LTC1416 VREF REFCOMP AGND
1416 F11b
R4 100 R5 R2 47k 50k R6 24k 22F
3 4 5
Figure 11b. Offset and Full-Scale Adjust Circuit
Generating a - 5V Supply There are several advantages to using 5V supplies rather than a single 5V supply. A larger signal magnitude is possible which increases the dynamic range and improves the signal-to-noise ratio. Operating on 5V supplies also offers increased headroom which eases the requirements for signal conditioning circuitry, avoids the limitations of rail-to-rail operation and widens the selection of high performance operational amplifiers. Some
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applications, however, do not have a -5V supply readily available and most ADCs have inadequate PSRR to sufficiently attenuate the noise created by a switching or charge pump supply. The LTC1416's excellent PSRR makes it possible to achieve good performance, even at 14 bits, using a switch based regulator for a -5V supply. Figure 12a shows a circuit using an LT1373 configured as a Cuk converter creating -5V from a 5V supply. The circuit shown in Figure 12b uses an LT1054 regulated charge pump to provide -5V. This circuit has the advantage of reduced board space and fewer passive components. (For further details refer to Linear Technology Magazine, June 1997, Page 29.) BOARD LAYOUT AND BYPASSING Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1416, a printed circuit board with ground plane is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. The analog input should be screened by AGND. An analog ground plane separate from the logic system ground should be established under and around the ADC (see Figure 13). Pin 5 (AGND), Pins 14 and 19 (ADC's DGND) and all other analog grounds should be connected to this single analog ground point. The REFCOMP bypass capacitor and the DVDD bypass capacitor should also be connected to this analog ground plane. No other digital grounds should be connected to this analog ground plane. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the foil width for these tracks should be as wide as possible. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a Wait state during conversion or by using three-state buffers to isolate the ADC data bus. The
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LTC1416
APPLICATIONS INFORMATION
5V C6 1 ANALOG INPUT 1F CER 2 3 4 C5 5 6 7 8 9 10 11 12 13 14 AIN+ AIN- VREF COMP AGND D13 (MSB) D12 D11 D10 D9 D8 D7 D6 DGND LTC1416 AVDD DVDD VSS BUSY CS CONVST RD SHDN D0 D1 D2 D3 D4 D5 28 27 26 25 24 23 22 21 20 19 18 17 16 15 C5 =22 F CERAMIC C6, C7 =10 F CERAMIC L1 =OCTAPAC CTX-100-1 D1 =1N5818 C9 0.01F MICROPROCESSOR/ MICROCONTROLLER INTERFACE C8 22F 10V TANT 5 CUK* CONVERTER 8 C11 100F 10V TANT R4 4.99k 1% D1 R3 4.99k R5 4.99k 1% R6 499 1%
1416 F12a
C10 10F CER
+
VIN S/S GND GND S U2 LT1373
VSW
4 7 6
NFB VC
3 1
Figure 12a. Using the LT1373 to Generate a - 5V Supply
C6 1 ANALOG INPUT 1F CER 2 3 4 C5 5 6 7 8 9 10 11 12 13 14 AIN+ AIN- VREF COMP AGND D13 (MSB) D12 D11 D10 LTC1416 D9 D8 D7 D6 DGND D1 D2 D3 D4 D5 AVDD DVDD VSS BUSY CS CONVST RD SHDN D0 28 27 C7 26 25 24 23 22 21 20 19 18 17 16 15 C5 =22 F CERAMIC C6, C7 =10 F CERAMIC C1 10F TANT MICROPROCESSOR/ MICROCONTROLLER INTERFACE 1 2 8 C2 2F FB/SHDN CAP+ V+ 7 OSC U1 LT1054 6 3 VREF GND 5 4 CAP - VOUT
C4 100F TANT
+
R1, 30.1k R2, 120k
1416 F12b
+
C3 0.002F
Figure 12b. Using the LT1054 to Generate a - 5V Supply
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+
C7
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2 L1 3
-5V
1
4
C12 0.1F
5V -5V
LTC1416
APPLICATIONS INFORMATION
1 AIN+ AIN- ANALOG INPUT CIRCUITRY REFCOMP 4 22F AGND 5 VSS 26 10F LTC1416 AVDD 28 10F DVDD 27 DGND 14 DIGITAL SYSTEM
+ -
2
Figure 13. Power Supply Grounding Practice.
traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC1416 has differential inputs to minimize noise coupling. Common mode noise on the AIN+ and AIN- leads will be rejected by the input CMRR. The AIN- input can be used as a ground sense for the AIN+ input; the LTC1416 will hold and convert the difference voltage between AIN+ and AIN- . The leads to AIN+ (Pin 1) and AIN- (Pin 2) should be kept as short as possible. In applications where this is not possible, the AIN+ and AIN- traces should be run side by side to equalize coupling. Supply Bypassing High quality, low series resistance ceramic, bypass capacitors should be used at the VDD (10F) and REFCOMP (22F) pins as shown in the Typical Application on the first page of this data sheet. Surface mount ceramic capacitors such as Murata GRM235Y5V106Z016 provide excellent bypassing in a small board space. Alternatively tantalum capacitors in parallel with 0.1F ceramic capacitors can be used. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. Example Layout Figures 14a, 14b, 14c and 14d show the schematic and layout of an evaluation board. The layout demonstrates the proper use of decoupling capacitors and ground plane with a 2-layer printed circuit board.
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1416 F13
DIGITAL INTERFACE The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. A separate CONVST is used to initiate a conversion. Internal Clock The A/D converter has an internal clock that eliminates the need for synchronization between the external clock and the CS and RD signals found in other ADCs. The internal clock is factory trimmed to achieve a typical conversion time of 1.8s, and a maximum conversion time over the full operating temperature range of 2.2s. No external adjustments are required. The guaranteed maximum acquisition time is 400ns. In addition, a throughput time of 2.5s and a minimum sampling rate of 400ksps is guaranteed. Power Shutdown The LTC1416 provides two power shutdown modes--nap mode and sleep mode to save power during inactive periods. The nap mode reduces the power by 95% and leaves only the digital logic and reference powered up. The wake-up time from nap to active is 200ns. In sleep mode the reference is shut down and only a small current of 120A remains. Wake-up time from sleep mode is much slower since the reference circuit must power up and settle to 0.005% for full 14-bit accuracy. Sleep mode wake-up time is dependent on the value of the capacitor connected to the REFCOMP (Pin 4). The wake-up time is 20ms with the recommended 22F capacitor.
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VCC VCC VLOGIC VSS 1 D[00:13] R0, 1.2k D0 D00 D01 D02 D03 D04 D05 D6 D7 R8, 1.2k R9, 1.2k D09 D10 D11 D12 D13 D8 D9 R10, 1.2k D10 R11, 1.2k D11 R12, 1.2k D12 R13, 1.2k D13 D06 D07 D08 D09 D10 D11 D12 D13 D00 D12 D11 17 Q2 Q3 D3 D4 7 8 9 D5 D6 D7 Q4 Q5 Q6 Q7 16 15 14 13 12 D10 D09 D08 D07 D06 D01 D02 D03 D04 D05 D06 D07 D08 D09 D13 VCC VSS U7E 11 HC14 U7C 5 DATA READY R20 1M C15 0.1F VLOGIC HC14 6 R21 1k C6 15pF 14 VCC 13 HC14
1416 F14a
U2 -VIN VIN VOUT GND D00 D01 D1 D2 D3 D4 D5 D02 D03 D04 D05 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 12 13 D13 14 D05 15 D04 16 D03 D08 17 D02 D07 18 D01 19 D00 D06 R6, 1.2k R7, 1.2k R5, 1.2k R4, 1.2k R3, 1.2k R2, 1.2k R1, 1.2k 2
LT1121-5
R14 20 U1 79L05
LTC1416
C2 22F 10V
C10 10F 10V
J2 VCC 1 B[00:13] 11 B00 B01 V+ B02 B03 B04 B05 B13 9 D7 U6 74HC574 1 11 B12 2 3 4 5 6 D2 D1 Q1 D0 18 Q0 19 B11 B10 B09 B08 B07 B06 0E J6-13 J6-14 J6-11 J6-12 J6-9 J6-10 J6-7 J6-8 J6-5 J6-6 D10 D11 10 D12 D13 U7D 9 HC14 8 D13 RDY J6-3 J6-4 J6-1 J6-2 J6-15 J6-16 J6-17 J6-18 U7F U7G HC14 GND 7 12 6 7 8 9 10 B09 11 B08 12 B07 13 B06 15 B05 16 B04 17 B03 18 B02 19 B01 20 B00 B10 B11 B12 B13 D6 U4 LTC1416 1 2 VREF 3 4 25 24 23 22 21 28 27 26 5 14 DGND D0 AGND D1 VSS D2 DVDD D3 AVDD D4 SHDN D5 RD D6 CONVST D7 CS D8 BUSY D9 REFCOMP D10 C13 22F 10 V VREF D11 AIN- D12 AIN+ D13 8 D5 7 D4 6 D3 5 D2 4 D1 3 D0 2 JP3 VOUT 0E C4 0.1F
GND
U5 74HC574
J4
JP2
R15 51
A+
R17 10k
U3 LT1363 27 - 6 3+ 8 1 4 V- VSS C3 0.1F
C11 1000pF
APPLICATIONS INFORMATION
A-
J5
LED D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D13 RDY DGND DGND HEADER 18-PIN JP1
C8 1F 10V
J7
CLK
1
U7A
2
3
U7B
4
R19 51
HC14
HC14
VLOGIC
JP5C
CS
JP5B
RD
C9 10F 10V C5 10F 10V
JP5A
SHDN
NOTES: UNLESS OTHERWISE SPECIFIED ALL RESISTOR VALUES IN OHMS, 5%
Figure 14a. Suggested Evaluation Circuit Schematic
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JP4
R16 51
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AGND
DGND
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+
16
J1 -7V TO -15V
+VIN
J3 7V TO 15V
1 C12 0.1F C14 0.1F
VIN
VOUT
3
GND TABGND 2 4
D15 SS12 5
+
D14 SS12
+
C1 22F 10V
LTC1416
APPLICATIONS INFORMATION
Figure 14b. Suggested Evaluation Circuit Board-- Component Side Silkscreen
Figure 14d. Suggested Evaluation Circuit Board-- Solder Side Layout
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Figure 14c. Suggested Evaluation Circuit Board-- Component Side Layout
CS t3 SHDN
1416 F15a
Figure 15a. CS to SHDN Timing
SHDN t3 CONVST
1416 F15b
Figure 15b. SHDN to CONVST Wake-Up Timing
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LTC1416
APPLICATIONS INFORMATION
Shutdown is controlled by Pin 21 (SHDN), the ADC is in shutdown when it is low. The shutdown mode is selected with Pin 20 (CS), low selects nap. Timing and Control Conversion start and data read operations are controlled by three digital inputs: CONVST, CS and RD. A logic "0" applied to the CONVST pin will start a conversion after the ADC has been selected (i.e., CS is low). Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY is low during a conversion. Figures 16 through 21 show several different modes of operation. In modes 1a and 1b (Figures 17 and 18) CS and RD are both tied low. The falling edge of CONVST starts the conversion. The data outputs are always enabled and data can be latched with the BUSY rising edge. Mode 1a shows operation with a narrow logic low CONVST pulse. Mode 1b shows a narrow logic high CONVST pulse. In mode 2 (Figure 19) CS is tied low. The falling edge of CONVST signal again starts the conversion. Data outputs are in three-state until read by the MPU with the RD signal. Mode 2 can be used for operation with a shared MPU data bus. In slow memory and ROM modes (Figures 20 and 21), CS is tied low and CONVST and RD are tied together. The MPU starts the conversion and reads the output with the RD signal. Conversions are started by the MPU or DSP (no external sample clock). In slow memory mode the processor applies a logic low to RD (= CONVST), starting the conversion. BUSY goes low, forcing the processor into a Wait state. The previous conversion result appears on the data outputs. When the conversion is complete, the new conversion results appear on the data outputs; BUSY goes high releasing the processor, and the processor takes RD (= CONVST) back high and reads the new conversion data. In ROM mode, the processor takes RD (= CONVST) low, starting a conversion and reading the previous conversion result. After the conversion is complete, the processor can read the new result and initiate another conversion.
CS = RD = 0
(SAMPLE N) t5 CONVST t6 BUSY t7 DATA DATA (N - 1) DB13 TO DB0 DATA N DB13 TO DB0 DATA (N + 1) DB13 TO DB0
1416 F17
Figure 17. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST = )
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CS t2 CONVST t1 RD
1416 F16
Figure 16. CS to CONVST Setup Timing
t CONV
t8
LTC1416
APPLICATIONS INFORMATION
CS = RD = 0 t13 CONVST t6 BUSY t7 DATA DATA (N - 1) DB13 TO DB0 DATA N DB13 TO DB0 DATA (N + 1) DB13 TO DB0
1416 F18
tCONV t5
Figure 18. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST = )
CS = 0
(SAMPLE N) tCONV t5
CONVST t6 BUSY t9 RD t 10 DATA DATA N DB13 TO DB0
1416 F19
Figure 19. Mode 2. CONVST Starts a Conversion. Data Is Read by RD
CS = 0 (SAMPLE N) RD = CONVST t6 BUSY t 10 DATA
t CONV
DATA (N - 1) DB13 TO DB0
Figure 20. Slow Memory Mode Timing
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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t8
t6
t6
t13 t8
t 12
t 11
t8
t 11
t7 DATA N DB13 TO DB0 DATA N DB13 TO DB0 DATA (N + 1) DB13 TO DB0
1416 F20
19
LTC1416
APPLICATIONS INFORMATION
CS = 0 (SAMPLE N) RD = CONVST t6 BUSY t 10 DATA DATA (N - 1) DB13 TO DB0 DATA N DB13 TO DB0
1416 F21
t CONV
t 11
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted. G Package 28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.397 - 0.407* (10.07 - 10.33) 28 27 26 25 24 23 22 21 20 19 18 17 16 15
0.205 - 0.212** (5.20 - 5.38)
0 - 8 0.301 - 0.311 (7.65 - 7.90) 0.002 - 0.008 (0.05 - 0.21)
0.005 - 0.009 (0.13 - 0.22)
0.022 - 0.037 (0.55 - 0.95)
0.0256 (0.65) BSC
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.010 - 0.015 (0.25 - 0.38)
RELATED PARTS
PART NUMBER LTC1278/LTC1279 LTC1400 LTC1409 LTC1410 LTC1412 LTC1415 LTC1418 LTC1419 LTC1604 LTC1605 DESCRIPTION Single Supply, 12-Bit, 500ksps/600ksps ADCs High Speed Serial 12-Bit ADC Low Power, 12-Bit, 800ksps Sampling ADC 12-Bit, 1.25Msps Sampling ADC with Shutdown 12-Bit, 3Msps Sampling ADC Single 5V, 12-Bit, 1.25Msps ADC 14-Bit, 200ksps Sampling ADC 14-Bit, 800ksps Sampling ADC with Shutdown 16-Bit, 333ksps Sampling ADC Single 5V, 16-Bit, 100ksps ADC COMMENTS Low Power, 5V or 5V Supply 400ksps, Complete with VREF, CLK, Sample-and-Hold in SO-8 Best Dynamic Performance, fSAMPLE 800ksps, 80mW Dissipation Best Dynamic Performance, THD = 84dB and SINAD = 71dB at Nyquist Best Dynamic Performance, SINAD = 72dB at Nyquist Single Supply, 55mW Dissipation 16mW Dissipation, Serial and Parallel Outputs 81.5dB SINAD, 150mW from 5V Supplies 2.5V Input, SINAD = 90dB, THD = 100dB Low Power, 10V Inputs
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
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Figure 21. ROM Mode Timing
0.068 - 0.078 (1.73 - 1.99)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
G28 SSOP 0694
1416f LT/TP 0598 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1997

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